The design cost in under 20nm processes has been increasing significantly due to the CMOS device scaling and its associated complications in design rules and device characteristics. Post-layout effects such as DIBL, WPE, and LOD significant affects the characteristics and design costs of analog and mixed-signal (AMS) circuits. Automation of AMS Circuit Design process can address these challenges by improving the design productivity. Our team is developing process-independent AMS circuit design automation techniques such as template-and-grid-based layout generation and RL-based circuit sizing.
Memory technologies are scaling down as logic technologies do, which requires porting of custom designs in every 2-3 years. Therefore, memory designs encounter similar problems with logic designs in advanced technology nodes, such as complicated design rules and device characteristics. Therefore, we are working on applying automation techniques to memory circuit design to enhance their design productivity.
Compact models are essential for integrated circuit design. Compact models are made up of math and physics and serve as a link between the design and process of integrated circuits. When a device with a new structure appears, the existing standard model cannot be applied, so a new compact model suitable for the device needs to be developed. However, it takes a considerable amount of time to develop an accurate model based on sophisticated physical equations. To address these challenges, our study presents a compact modeling methodology based on machine learning.