Most of EDA algorithms are sequential, so the designing order highly affects the next design step and final quality of result. In the detailed placement step, more than thousands of cells should be ordered for the sequential algorithm. However, finding the best designing order is very complex and time-consuming due to the number of cells and the variance for each design. Using the reinforcement learning, we can find the optimal designing order for each of various designs. RL framework can improve the solution quality of detailed placement.
The increase of routing complexity in advanced technology nodes incurs the miscorrelation between pre-route design rule violation (DRV) prediction and actual post-route DRV, causing additional iterations during design implementation, which causes design time increase. Our pre-route DRV predictor is based on the combination of fully convolutional network (FCN) and graph neural network (GNN) to efficiently capture the global routing congestion and the pin accessibility which are the two fundamental causes of DRV. Next, placement improvement guided by DRV prediction in placement is provided within the predicted hotspot region to optimize the DRV by cell shifting, flipping and swapping based on more accurate DRV prediction.
In the advanced technology nodes, the gap between the predicted pre-route path delay and the actual post-route path delay becomes huge, which hinders the physical design flow from the convergence of a design to an optimal solution with perfect timing closure. We propose a 2-step solution to overcome this problem that is fully compatible with the commercial P&R tools. First, we present a CNN-based model to predict wire delay and slew in the pre-route stage. Second, we integrate our prediction into the commercial P&R tools as a zero-overhead plug-in to better correlate the pre-/post-route path delay and enable the P&R tools to converge faster to the final design result with better quality-of-results.
Placement & Routing(P&R) is most expensive and painful task for chip implementation in advanced technology nodes. P&R flow consists of multiple SW modules and each SW module has lots of tool parameters to be set. Also, there are design and flow parameters to be tuned for specific chip implementation. The search space for the optimum solution in these tool, design, flow parameters will be over 1 trillion design technology recipes. So, it is impossible to get optimum or even sub-optimum solution within reasonable time. In this project, we will develop DSO SW using Reinforcement Learning which enables chip PPA(power, performance, area) optimization with small cost (man-power x time).
PDN is responsible for supplying the current from power pads to active circuits (or draining the current from active circuits to ground pads), while the constraint on IR drop is respected. A popular PDN synthesis method is to assume regular PDN before placement and routing are performed. Strap widths and pitches are determined in empirical fashion through evaluation of a number of test designs, but only in conservative fashion. On the other hand, we consider PDN synthesis for a particular circuit after its placement has been performed, where ML model iteratively determines the best location of PDN strap in terms of IR drop and routing congestion. The resulting PDN will show the better routability while satisfying IR drop constraint, compared to regular PDN.