Usually, the best cache & interconnect design is determined after exhaustively simulating, which costs lots of time and money. AI-based cache & interconnect automation technologies are needed to reduce the waste of human resources. For cache design, the task is to develop an ANN that outputs the optimal cache configuration (hierarchy, size, level, etc.) after analyzing the cache access pattern. It provides a fast prediction for the miss rate curve. For on-chip interconnect design, the task is to propose a GNN model that inputs communication patterns between accelerators. It profiles the communication requirements between each nodes and derives the optimal interconnect architecture.

The complete optimization engine can be described as:  (1) building a practical reinforcement learning environment and integrating the network model proposed in the [Interworking circuit recognition network and reinforcement learning framework] section.  (2) building test benchmarks, and (3) building real reinforcement learning environment  for circuit optimization engine by using a real circuit database generated from STA tool, and integrating with reinforcement learning engine.

Multi-chiplet architectures provide lower cost alternative and reduce design time. Currently few players in the semiconductor industry consider multi-chiplet design but it seem to be growing increasingly. Before integration of chiplet into system, the feasibility analysis in early design stage is required to avoid design iteration. In 2.5D and 3D IC design approach, the ASIC components are to be stacked and interconnected and the IO planning is key issue for integration of multi-chiplets. ML based multi-chiplet IO planning provides connectivity analysis and optimal IO planning features. The optimal positioning of C4 and micro bump with design constraints allows designers to analysis feasibility in early design stage and to reduce design iteration.

Optimal IO Planning is an iterative and time-consuming process in System-on-Chip(SoC) design. In traditional design flow, the optimal IO planning depends on designers’ experience and Electronic Design Automation(EDA) tool for automatic IO planning is not provided. To reduce chip size in SoC design, the IO placement on multiple IO row considering R이 routing is essential but existing placement algorithm is not suitable for applying to optimal IO placement which contains various constraints. Proposed ML based IO planning enables designers to optimize IO placement on multiple IO row automatically and to reduce unexpected design iteration dramatically. The result of IO planning with 3rd party EDA tool interface fills the gap between chip and PKG design.

Early-stage (e.g. RTL) design impacts final design quality, which necessitates accurate early-stage design analysis for optimized results. Absence of physical information, however, degrades correlation between analyzed results of early-stage and after actual physical design. Trial floorplanner, a quick placer for early-stage design, can offer useful information to obtain better analysis results, which guides to enhancement of design quality. Our trial floorplanner, based on ML model for graph analysis, extracts implicit block groups from given floorplan data by connectivity and application of blocks. Blocks of new design can be grouped using extracted knowledge to obtain floorplan data.

Collecting a large amount of EDA data such as circuit benchmarks and physical layout designs is one of the most challenges in ML-EDA research. The main goal of data augmentation flow for EDA research is to prepare `unseen’ circuit designs in advance by exploring the topological characteristics from the existing real-world circuit designs, it can improve the feature coverage of layout database. In this flow, we use an artificial netlist generator to generate an artificial synthetic circuit from the user-specified input parameters representing the topological shape of circuit. This flow increases the diversity of topological shape of the existing circuits so that exploration on various features related to circuit characteristics can be possible.